080290038 VLSI Design ECE 6th Semester Anna University Coimbatore Syllabus Regulation 2008

Anna university Coimbatore Syllabus

080290038 VLSI Design ECE 6th Semester Anna University Coimbatore Syllabus Regulation 2008

Department of Electronics and Communication Engineering 

Meant for Anna University Coimbatore

Syllabus 

(Regulation 2008/2010)

___________________________________________________________________________________

Details:

University:Anna University

Year: Third Year

Department: B.E Electronics and Communication Engineering 

Semester:  (VI) 

Content: 080290038 VLSI Design ECE 6th Semester Anna University Coimbatore Syllabus Regulation 2008

Post Type: Syllabus

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UNIT I MOS TECHNOLOGY                                         

Chip Design Hierarchy- IC Layers –Photolithography and Pattern Transfers- Basic

MOS Transistors-CMOS Fabrication – Submicron CMOS Process –Masks and Layout

–CMOS Design Rules: Lambda based layout- Types of rules- SCMOS Design Rule set

II-

UNIT II  MOSFET TRANSISTOR                                                                            9

MOSFET operation -  MOSFET switch  model  and  square law  model  –  MOSFET parasitic-– MOSFET SPICE Modeling-CMOS Inverter: Voltage Transfer curve- Layout- Body Effect-Latch up problem in CMOS circuits-Latch up prevention-

UNIT III          CMOS LOGIC GATES DESIGN AND LAYOUT                                    

NAND and NOR Gates – Complex Logic Gates –Tri state circuits – Large FETs- Transmission Gate and Pass Transistor Logic-Standard Cell design: Cell hierarchy- Cell libraries-

UNIT IV          STORAGE ELEMENTS AND DYNAMIC LOGIC CIRCUITS             9

SR Latch- Bit Level Register –D Type Flip Flop –Dynamic D Flip Flop –The Static RAM Cell –Dynamic Logic – Domino Logic – SR Logic –Dynamic Memories

UNIT V VHDL                                                                                                             9

VHDL Program Structure- concurrent code – sequential code - Variables- signals and Constants-VHDL Operators -VHDL Description of Combinational Networks: Adders – Modeling Flip Flop using VHDL Processes – VHDL Model for Multiplexer –Modeling a sequential Machine-

TOTAL: 45

TUTORIAL : 15

TEXT BOOKS:

1-  John  P  Uyemura-  “  Chip  Design  for  Submicron  VLSI:CMOS  layout  and simulation” Thomson India Edition- 2006(unit I to IV)

2-  Charles  H  Roth-”Digital  System  Design  Using  VHDL”-  Thomson  business

Information India Pvt Ltd-2006 (Unit V)

REFERENCES

3-  Kamran Eshraghian- Douglas A Pucknell Sholeh Eshraghian “Essentials of VLSI Circuits and Systems”- Prentice Hall of India Pvt Ltd- 2006

4-  Volnei A Pedroni-”Circuit design with VHDL”- Prentice Hall of India Pvt Ltd-

2005

5    Wayne Wolf,” Modern VLSI Design – System On Chip”, PHI 2006, 3e, New Delhi

ATTACHMENT    Download

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